FIG. 1 is a schematic circuit diagram illustrating a conventional level shifter. By the level shifter 100, an input signal IN and an inverted input signal ZIN in the range between a voltage Vd and the voltage GND are changed to an output voltage OUT and an inverted output voltage ZOUT in the range between a voltage Vp and the voltage GND. The voltage Vd is a power supply voltage (e.g., 1.2V), the voltage Vp is another power supply voltage (e.g., 5V), and the voltage GND is a ground voltage (e.g., 0V). The input signal IN and the inverted input signal ZIN are complementary signals. The output voltage OUT and the inverted output voltage ZOUT are complementary signals.
As shown in FIG. 1, the level shifter 10 comprises a P-type transistor MP1, a P-type transistor MP2, an N-type transistor MN1, and an N-type transistor MN2. The source terminal of the P-type transistor MP1 receives the power supply voltage Vp. The drain terminal of the P-type transistor MP1 is connected with a node “a”. The gate terminal of the P-type transistor MP1 is connected with a node “b”. The source terminal of the P-type transistor MP2 receives the power supply voltage Vp. The drain terminal of the P-type transistor MP2 is connected with the node “b”. The gate terminal of the P-type transistor MP2 is connected with the node “a”.
The drain terminal of the N-type transistor MN1 is connected with the node “a”. The source terminal of the N-type transistor MN1 is connected with the ground voltage GND. The gate terminal of the N-type transistor MN1 receives the input signal IN. The drain terminal of the N-type transistor MN2 is connected with the node “b”. The source terminal of the N-type transistor MN2 is connected with the ground voltage GND. The gate terminal of the N-type transistor MN2 receives an inverted input signal ZIN. The node “b” is served as a first output terminal to output the output signal OUT. The node “a” is served as a second output terminal to output the inverted output signal ZOUT.
In case that the input signal IN is in a first high level state corresponding to the power supply voltage Vd (e.g., 1.2V) and the inverted input signal ZIN is in a low level state (e.g., 0V), the N-type transistor MN1 and the P-type transistor MP2 are turned on, and the N-type transistor MN2 and the P-type transistor MP1 are turned off. Consequently, the output signal OUT is in a second high level state corresponding to the power supply voltage Vp (e.g., 5V), and the inverted output signal ZOUT is in the low level state (e.g., 0V).
In case that the input signal IN is in the low level state (e.g., 0V) and the inverted input signal ZIN is in the first high level state corresponding to the power supply voltage Vd (e.g., 1.2V), the N-type transistor MN1 and the P-type transistor MP2 are turned off, and the N-type transistor MN2 and the P-type transistor MP1 are turned on. Consequently, the output signal OUT is in the low level state (e.g., 0V), and the inverted output signal ZOUT is in the second high level state corresponding to the power supply voltage Vp (e.g., 5V).
At the moment when the input signal IN is switched from the first high level state to the low level state (i.e., when the inverted input signal ZIN is switched from the low level state to the first high level state), the N-type transistor MN1 is turned off, the N-type transistor MN2 is turned on, and the P-type transistor MP1 is turned on. However, the P-type transistor MP2 is still turned on and not completely turned off. Under this circumstance, the level shifter 100 enters a short fighting period until the P-type transistor MP2 is completely turned off.
Similarly, at the moment when the input signal IN is switched from the low level state to the first high level state (i.e., when the inverted input signal ZIN is switched from the first high level state to the low level state), the P-type transistor MP1 is still turned on and not completely turned off. Under this circumstance, the level shifter 100 enters a short fighting period until the P-type transistor MP1 is completely turned off.
Generally, the driving strength of the P-type transistor is related to the channel length and the channel width of the P-type transistor. In case that the P-type transistor has a wider channel width and a shorter channel length, the P-type transistor has the higher driving strength. Whereas, in case that the P-type transistor has a narrower channel width and a longer channel length, the P-type transistor has the lower driving strength.
For shortening the fighting period of the level shifter 100, the power supply voltage Vp needs to be taken into consideration when the level shifter 100 is designed. Generally, in case that the magnitude of the power supply voltage Vp is lower (e.g., 1.5V), the driving strengths of the P-type transistor MP1 and the P-type transistor MP2 are designed to be as strong as possible. Whereas, in case that the magnitude of the power supply voltage Vp is higher (e.g., 5V), the driving strengths of the P-type transistor MP1 and the P-type transistor MP2 are designed to be as weak as possible.
However, it is difficult for the level shifter 100 to utilize the power supply voltage Vp in a wide range. For example, the level shifter 100 using the 1.5V power supply voltage Vp is not suitably operated at the 6V power supply voltage Vp.